1. Field of the Invention
The present invention relates to a PC(Personal Computer) and ATE(Automatic Test Equipment) integrated chip test equipment, and in particular to a PC and ATE integrated chip test equipment which is capable of generating a pattern test using a PC test and a pattern generation board for a semiconductor chip test and outputting to a memory for thereby concurrently performing two processes in one equipment based on an integrated automatic test.
2. Description of the Background Art
FIG. 1 is a view illustrating the construction of a system in which an equipment for testing a memory module during a PC test in the conventional art(Korean Lain-open Number 2002-0004387).
The above system includes a programmable power voltage supply unit 110 for setting a VIH/VIL level to a user's level and supplying the same, a level checking unit 120 for reading a voltage for checking the changed level, an address input unit 130 for designating an address of a memory which will be tested before a memory module test is performed and selecting an I/O address of a board to which the voltage levels of the VIH and VIL are applied, a signal selection unit 140 for receiving an output signal which selects an I/O address of a board to which the voltage levels of the VIH and VIL are applied from the address input unit 130 and selectively outputting a changed level voltage from the power voltage supply unit 110 and a normal state voltage from a chip set unit 200, a test result checking unit 150 for judging whether the test is passed or failed as a result of the test, a chip set unit 200 for applying a normal state voltage, and a memory module unit 300 for performing a test.
The level checking unit 120 is formed of 12-bit and includes an analog/digital converter capable of reading a 4-bit first and then reading the remaining 8-bit.
When the test is started, an externally applied voltage is changed to a voltage of a user's VIH and VIL level by the power voltage supply equipment 110. In order to check the changed voltage level, the level checking unit 120 formed of the analog/digital converter checks the changed voltage level, and the changed voltage level is applied to the signal selection unit 140.
Next, the signal selection unit 140 receives an address of a memory, which will be tested in the address input unit 130 and an I/O address of a board to which the changed VIH and VIL voltage levels are applied, from a first output signal(A) and a second output signal(B), respectively. Thereafter, the signal selection unit 140 selectively applies a normal state voltage and a changed level voltage to the memory module unit 300 for thereby performing a test.
In the above system, when a PC test of the memory module is performed, the voltage levels of the VIH and VIL of the signals applied to the memory are programmable-changed, so that it is judged whether the test of the memory is passed or failed at the PC level. Since the memory controller which is called as a chip set, can not directly access a memory without a CPU instruction which is allowed by the PC, the address of the memory which will be tested, must be designated before the memory module test is performed. Therefore, there are many problems for accessing a desired data at a certain address and a certain timing for implementing an accurate test of a chip.
FIG. 2 is a block diagram illustrating a system for explaining a test method of a chip equipment in a conventional art(Korean Laid-open Number 2001-0062640).
The above chip equipment includes a PC equipment 201 having a chip equipment 210, a logic analyzer 202 for trigging and obtaining a signal waveform of a terminal(pin) group of the chip equipment 210 as a certain fail information, a pattern generation equipment 203 for inputting a signal waveform data(trace data) obtained from the logic analyzer 202 and converting to a test pattern of a desired test equipment and outputting the same, an automatic test equipment(ATE) 204 for testing a chip equipment as a tested device(DUT) 204-1 using a test pattern from the pattern generation equipment 203 and judging whether an error occurs in the PC equipment, and a mass production ATE 205 for testing the products same as the chip equipment 210 mounted in the PC equipment 201 as a tested device(DUT) 205-1.
In the above conventional art, a test pattern is generated based on a trace data of an operation state of a chip equipment mounted in a PC equipment for thereby testing a tested device.
A data extracted from a logic analyzer is capable of only a small amount of a timing pattern which occurs in the PC. Even when a desired amount of the timing pattern is extracted, since the environments between the PC and the ATE are very different, a desired reproduction is not obtained. In addition, the above system is so expensive.